Interrupt Status Register 1
| TO_HS_TX | This bit indicates that the high-speed transmission timeout counter reached the end and contention has been detected. |
| TO_LP_RX | This bit indicates that the low-power reception timeout counter reached the end and contention has been detected. |
| ECC_SINGLE_ERR | This bit indicates that the ECC single error has been detected and corrected in a received packet. |
| ECC_MILTI_ERR | This bit indicates that the ECC multiple error has been detected in a received packet. |
| CRC_ERR | This bit indicates that the CRC error has been detected in the received packet payload. |
| PKT_SIZE_ERR | This bit indicates that the packet size error has been detected during the packet reception. |
| EOPT_ERR | This bit indicates that the EoTp packet has not been received at the end of the incoming peripheral transmission. |
| DPI_PLD_WR_ERR | This bit indicates that during a DPI pixel line storage, the payload FIFO becomes full and the data stored is corrupted. |
| GEN_CMD_WR_ERR | This bit indicates that the system tried to write a command through the Generic interface and the FIFO is full. Therefore, the command is not written. |
| GEN_PLD_WR_ERR | This bit indicates that the system tried to write a payload data through the Generic interface and the FIFO is full. Therefore, the payload is not written. |
| GEN_PLD_SEND_ERR | This bit indicates that during a Generic interface packet build, the payload FIFO becomes empty and corrupt data is sent. |
| GEN_PLD_RD_ERR | This bit indicates that during a DCS read data, the payload FIFO becomes empty and the data sent to the interface is corrupted. |
| GEN_PLD_RECEV_ERR | This bit indicates that during a generic interface packet read back, the payload FIFO becomes full and the received data is corrupted. |
| DPI_BUFF_PLD_UNDER | This bit indicates that an underflow has occurred when reading payload to build DSI packet for video mode. |